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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-17 12:10:19 +0100 |
| commit | c06c062469a6f5ea16116a5ed3bc4a45b6e818a2 (patch) | |
| tree | ea54f3510f2e85771422718385028b0864696cba /frontends/ast/genrtlil.cc | |
| parent | 8ddec5d882c6834cb6b3415e05a2a88d416cabff (diff) | |
| parent | e45f62b0c56717a23099425f078d1e56212aa632 (diff) | |
| download | yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.gz yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.tar.bz2 yosys-c06c062469a6f5ea16116a5ed3bc4a45b6e818a2.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 9531dd356..e66625228 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -942,16 +942,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node case AST_CONSTANT: + case AST_REALVALUE: { if (width_hint < 0) detectSignWidth(width_hint, sign_hint); - is_signed = sign_hint; - return RTLIL::SigSpec(bitsAsConst()); - } - case AST_REALVALUE: - { + if (type == AST_CONSTANT) + return RTLIL::SigSpec(bitsAsConst()); + RTLIL::SigSpec sig = realAsConst(width_hint); log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig)); return sig; |