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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-10 13:19:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-10 13:19:04 +0200 |
| commit | db98a18edb02a5c3a0c3f26efec0e01f8232790a (patch) | |
| tree | 2f1d2758fe775d7d39b0a09561525681f9c6452f /frontends/ast/genrtlil.cc | |
| parent | af79b4bd9827ec0c8aff284a44e861ab0d0efff1 (diff) | |
| download | yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.tar.gz yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.tar.bz2 yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.zip | |
Enabled AST/Verilog front-end optimizations per default
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index cb57bbab7..1fb762fc1 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -628,6 +628,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) // shifter cell is created and the output signal of this cell is returned case AST_IDENTIFIER: { + RTLIL::Wire *wire = NULL; + RTLIL::SigChunk chunk; + if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires.count(str) == 0) { RTLIL::Wire *wire = new RTLIL::Wire; wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); @@ -643,6 +646,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) wire->auto_width = true; current_module->wires[str] = wire; } + else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { + chunk = RTLIL::Const(id2ast->bits); + goto use_const_chunk; + } else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE && id2ast->type != AST_MEMORY) || current_module->wires.count(str) == 0) log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n", @@ -652,13 +659,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint) log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n", str.c_str(), filename.c_str(), linenum); - RTLIL::Wire *wire = current_module->wires[str]; - - RTLIL::SigChunk chunk; + wire = current_module->wires[str]; chunk.wire = wire; chunk.width = wire->width; chunk.offset = 0; + use_const_chunk: if (children.size() != 0) { assert(children[0]->type == AST_RANGE); if (!children[0]->range_valid) { |