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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-12 01:15:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-12 01:15:37 +0200 |
| commit | ded769c98cffe5682c0211dba08abc4a1efe3d5a (patch) | |
| tree | 04e2f69dd3f943996f2cb1098bcac0de91e0ef68 /frontends/ast/genrtlil.cc | |
| parent | 3cd97a205f30e9c0671b3a909f3371fe02e0f0b2 (diff) | |
| download | yosys-ded769c98cffe5682c0211dba08abc4a1efe3d5a.tar.gz yosys-ded769c98cffe5682c0211dba08abc4a1efe3d5a.tar.bz2 yosys-ded769c98cffe5682c0211dba08abc4a1efe3d5a.zip | |
Fixed sign handling in ternary operator
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 791ee9867..a9574254d 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1007,8 +1007,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = std::max(val1.width, val2.width); is_signed = children[1]->is_signed && children[2]->is_signed; - val1.extend(width); - val2.extend(width); + val1.extend(width, is_signed); + val2.extend(width, is_signed); return mux2rtlil(this, cond, val1, val2); } |