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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-14 05:24:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-10-14 05:24:31 +0200 |
| commit | e84cedfae4211244da45ef51a84213874579117e (patch) | |
| tree | fb0a14f4c06675a7d3dbb5a1f22d386402e22d0b /frontends/ast/genrtlil.cc | |
| parent | 3c6a566d865e3d70f8793225a6d211ce3d6246a1 (diff) | |
| parent | e46e8753c84ee83f871d5ce116ce4c08dd49a031 (diff) | |
| download | yosys-e84cedfae4211244da45ef51a84213874579117e.tar.gz yosys-e84cedfae4211244da45ef51a84213874579117e.tar.bz2 yosys-e84cedfae4211244da45ef51a84213874579117e.zip | |
Use "(id)" instead of "id" for types as temporary hack
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 407a34472..94f5c0a04 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -863,6 +863,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_PACKAGE: case AST_MODPORT: case AST_MODPORTMEMBER: + case AST_TYPEDEF: break; case AST_INTERFACEPORT: { // If a port in a module with unknown type is found, mark it with the attribute 'is_interface' |