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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-27 13:50:08 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-27 13:50:08 +0100 |
| commit | ecc30255ba70910777a4586f5bd6abc818073293 (patch) | |
| tree | 35eb7e1b849d1da91c5ab5e2ffd4251aeb8a213d /frontends/ast/genrtlil.cc | |
| parent | 11ffa7867794ee5bda2742830bda64976ad4f549 (diff) | |
| download | yosys-ecc30255ba70910777a4586f5bd6abc818073293.tar.gz yosys-ecc30255ba70910777a4586f5bd6abc818073293.tar.bz2 yosys-ecc30255ba70910777a4586f5bd6abc818073293.zip | |
Added proper === and !== support in constant expressions
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 269752df5..36ca1432b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -728,6 +728,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint) case AST_LE: case AST_EQ: case AST_NE: + case AST_EQX: + case AST_NEX: case AST_GE: case AST_GT: width_hint = std::max(width_hint, 1); @@ -1113,12 +1115,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt - if (0) { case AST_LT: type_name = "$lt"; } - if (0) { case AST_LE: type_name = "$le"; } - if (0) { case AST_EQ: type_name = "$eq"; } - if (0) { case AST_NE: type_name = "$ne"; } - if (0) { case AST_GE: type_name = "$ge"; } - if (0) { case AST_GT: type_name = "$gt"; } + if (0) { case AST_LT: type_name = "$lt"; } + if (0) { case AST_LE: type_name = "$le"; } + if (0) { case AST_EQ: type_name = "$eq"; } + if (0) { case AST_NE: type_name = "$ne"; } + if (0) { case AST_EQX: type_name = "$eq"; } + if (0) { case AST_NEX: type_name = "$ne"; } + if (0) { case AST_GE: type_name = "$ge"; } + if (0) { case AST_GT: type_name = "$gt"; } { int width = std::max(width_hint, 1); width_hint = -1, sign_hint = true; |