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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-22 17:18:59 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 20:06:00 +0200 |
| commit | 24b880b2de1676b420f5a0bbdf3805dab38b8f00 (patch) | |
| tree | 5d71ef2f4389ca661861b223bcde08227d6e057f /frontends/ast/simplify.cc | |
| parent | 097de6c5f8c5170cc275b7250bf3780ae6ab3a00 (diff) | |
| download | yosys-24b880b2de1676b420f5a0bbdf3805dab38b8f00.tar.gz yosys-24b880b2de1676b420f5a0bbdf3805dab38b8f00.tar.bz2 yosys-24b880b2de1676b420f5a0bbdf3805dab38b8f00.zip | |
kernel/mem: Add model support for read port init value and resets.
Like wide port support, this is still completely unusable, and support
in various passes will be gradually added later. It also has no support
at all in the cell library, so attempting to create a read port with
a reset or initial value will cause an assert failure for now.
Diffstat (limited to 'frontends/ast/simplify.cc')
0 files changed, 0 insertions, 0 deletions