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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 20:58:37 +0200 |
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| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 21:11:48 +0200 |
| commit | 458a94059e6738d93a87ddb9af282d0e1d28791d (patch) | |
| tree | 7d2e8430a312360dd5d7049850b5493eb1dc1734 /frontends/ast/simplify.cc | |
| parent | 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 (diff) | |
| download | yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.tar.gz yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.tar.bz2 yosys-458a94059e6738d93a87ddb9af282d0e1d28791d.zip | |
Support for 'modports' for System Verilog interfaces
Diffstat (limited to 'frontends/ast/simplify.cc')
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