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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-18 10:58:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-18 10:58:47 +0200 |
| commit | f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c (patch) | |
| tree | 1778829a6932d18730a3a085a80a65205189c7ba /frontends/ast/simplify.cc | |
| parent | 24a5c6585678f89058382fe2c3f36b821b419e90 (diff) | |
| parent | 736105b0468f9468f00915cad60949535ce5a496 (diff) | |
| download | yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.gz yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.tar.bz2 yosys-f24bc1ed0a80e48bc23ae68169b6b0bbce5f113c.zip | |
Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
Diffstat (limited to 'frontends/ast/simplify.cc')
| -rw-r--r-- | frontends/ast/simplify.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index dca9da198..e56a62563 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -71,7 +71,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (stage == 0) { - log_assert(type == AST_MODULE); + log_assert(type == AST_MODULE || type == AST_INTERFACE); last_blocking_assignment_warn = pair<string, int>(); deep_recursion_warning = true; |