Added support for SystemVerilog packages with localparam definitions

3 files changed, 16 insertions, 1 deletions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 3ba97ed9b..ba02dd4c5 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -151,6 +151,7 @@ std::string AST::type2str(AstNodeType type)
 	X(AST_POSEDGE)
 	X(AST_NEGEDGE)
 	X(AST_EDGE)
+	X(AST_PACKAGE)
 #undef X
 	default:
 		log_abort();
@@ -996,6 +997,14 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			for (auto n : global_decls)
 				(*it)->children.push_back(n->clone());
 
+			for (auto n : design->packages){
+				for (auto o : n->children) {
+					AstNode *cloned_node = o->clone();
+					cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
+					(*it)->children.push_back(cloned_node);
+				}
+			}
+
 			if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
 				(*it)->str = (*it)->str.substr(1);
 
@@ -1013,6 +1022,9 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 
 			design->add(process_module(*it, defer));
 		}
+		else if ((*it)->type == AST_PACKAGE){
+			design->packages.push_back((*it)->clone());
+		}
 		else
 			global_decls.push_back(*it);
 	}
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 21c3ba3c6..3dcd32bd4 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -137,7 +137,9 @@ namespace AST
 
 		AST_POSEDGE,
 		AST_NEGEDGE,
-		AST_EDGE
+		AST_EDGE,
+
+		AST_PACKAGE
 	};
 
 	// convert an node type to a string (e.g. for debug output)
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 0e5029eb4..3e359170b 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -806,6 +806,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_GENBLOCK:
 	case AST_GENIF:
 	case AST_GENCASE:
+	case AST_PACKAGE:
 		break;
 
 	// remember the parameter, needed for example in techmap