Added read_verilog -icells option

3 files changed, 11 insertions, 5 deletions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 20720051a..40f7826f1 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -46,7 +46,7 @@ namespace AST {
 
 // instanciate global variables (private API)
 namespace AST_INTERNAL {
-	bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
+	bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
 	AstNode *current_ast, *current_ast_mod;
 	std::map<std::string, AstNode*> current_scope;
 	RTLIL::SigSpec *genRTLIL_subst_from = NULL;
@@ -826,11 +826,12 @@ static AstModule* process_module(AstNode *ast)
 	current_module->mem2reg = flag_mem2reg;
 	current_module->lib = flag_lib;
 	current_module->noopt = flag_noopt;
+	current_module->icells = flag_icells;
 	return current_module;
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool ignore_redef)
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef)
 {
 	current_ast = ast;
 	flag_dump_ast1 = dump_ast1;
@@ -841,6 +842,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 	flag_mem2reg = mem2reg;
 	flag_lib = lib;
 	flag_noopt = noopt;
+	flag_icells = icells;
 
 	assert(current_ast->type == AST_DESIGN);
 	for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
@@ -877,6 +879,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
 	flag_mem2reg = mem2reg;
 	flag_lib = lib;
 	flag_noopt = noopt;
+	flag_icells = icells;
 	use_internal_line_num();
 
 	std::string para_info;
@@ -959,6 +962,7 @@ RTLIL::Module *AstModule::clone() const
 	new_mod->mem2reg = mem2reg;
 	new_mod->lib = lib;
 	new_mod->noopt = noopt;
+	new_mod->icells = icells;
 
 	return new_mod;
 }
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 14e7803bf..caae679a1 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -231,13 +231,13 @@ namespace AST
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool ignore_redef = false);
+	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool icells = false, bool ignore_redef = false);
 
 	// parametric modules are supported directly by the AST library
 	// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
 	struct AstModule : RTLIL::Module {
 		AstNode *ast;
-		bool nolatches, nomem2reg, mem2reg, lib, noopt;
+		bool nolatches, nomem2reg, mem2reg, lib, noopt, icells;
 		virtual ~AstModule();
 		virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
 		virtual RTLIL::Module *clone() const;
@@ -258,7 +258,7 @@ namespace AST
 namespace AST_INTERNAL
 {
 	// internal state variables
-	extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
+	extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
 	extern AST::AstNode *current_ast, *current_ast_mod;
 	extern std::map<std::string, AST::AstNode*> current_scope;
 	extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 83a5c7506..6001e278a 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1334,6 +1334,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				AstNode *child = *it;
 				if (child->type == AST_CELLTYPE) {
 					cell->type = child->str;
+					if (flag_icells && cell->type.substr(0, 2) == "\\$")
+						cell->type = cell->type.substr(1);
 					continue;
 				}
 				if (child->type == AST_PARASET) {