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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 10:55:41 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-04 10:55:41 -0700 |
| commit | 3c462e5eeb5d24f5252bc1e7437f91372ec48fd0 (patch) | |
| tree | 0d7524842086e84cb266b6a6e8dac54afe349d2c /frontends/ast | |
| parent | 58af64b63a3a253ab08b1410422677deac5c6618 (diff) | |
| parent | d2306d7b1d9725fef2d1db4e205c1b0cb6c84715 (diff) | |
| download | yosys-3c462e5eeb5d24f5252bc1e7437f91372ec48fd0.tar.gz yosys-3c462e5eeb5d24f5252bc1e7437f91372ec48fd0.tar.bz2 yosys-3c462e5eeb5d24f5252bc1e7437f91372ec48fd0.zip | |
Merge pull request #1338 from YosysHQ/eddie/deferred_top
hierarchy -auto-top to work with (* top *) modules from read/read_verilog -defer
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 82283fb5b..a3a78e414 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1099,6 +1099,13 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast ignoreThisSignalsInInitial = RTLIL::SigSpec(); } + else { + for (auto &attr : ast->attributes) { + if (attr.second->type != AST_CONSTANT) + continue; + current_module->attributes[attr.first] = attr.second->asAttrConst(); + } + } if (ast->type == AST_INTERFACE) current_module->set_bool_attribute("\\is_interface"); |