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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-27 22:44:01 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-27 22:44:01 +0200 |
| commit | 516e8828f2e1175b449e45879d19d20e080e2398 (patch) | |
| tree | b55387494d6945ab65288e3beafe42a891fa5736 /frontends/ast | |
| parent | 4d0ba9b3b27d507ba032bdc1a4bcbf63e2581336 (diff) | |
| download | yosys-516e8828f2e1175b449e45879d19d20e080e2398.tar.gz yosys-516e8828f2e1175b449e45879d19d20e080e2398.tar.bz2 yosys-516e8828f2e1175b449e45879d19d20e080e2398.zip | |
Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
Diffstat (limited to 'frontends/ast')
0 files changed, 0 insertions, 0 deletions