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authorEddie Hung <eddie@fpgeh.com>2020-05-05 06:49:18 -0700
committerGitHub <noreply@github.com>2020-05-05 06:49:18 -0700
commit7a62ee57b4953a01637086d409a99b9779a7d6c9 (patch)
tree65e5a6c22a393ca75421e135bf02e725f45aa9d8 /frontends/ast
parent99aff5a0f9f322bf4498fe06094de9919ed56681 (diff)
parenteca9fc01a78c5cc4c1d8120e2ccdf18211bcef37 (diff)
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Merge pull request #2024 from YosysHQ/eddie/primitive_src
verilog: set src attribute for primitives
Diffstat (limited to 'frontends/ast')
-rw-r--r--frontends/ast/simplify.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 837c14ad7..488681649 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1739,8 +1739,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *node = children_list[1];
if (op_type != AST_POS)
- for (size_t i = 2; i < children_list.size(); i++)
+ for (size_t i = 2; i < children_list.size(); i++) {
node = new AstNode(op_type, node, children_list[i]);
+ node->location = location;
+ }
if (invert_results)
node = new AstNode(AST_BIT_NOT, node);