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| author | Clifford Wolf <clifford@clifford.at> | 2016-11-15 12:42:43 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-11-15 12:42:43 +0100 |
| commit | a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51 (patch) | |
| tree | effa1745fb6b7c2320455c2d4f7c58171e8edab1 /frontends/ast | |
| parent | a2206180d60c857578209300c3a693e9c4723459 (diff) | |
| download | yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.tar.gz yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.tar.bz2 yosys-a926a6afc2cf6ab7aed2c18950c6cd38d21f2a51.zip | |
Remember global declarations and defines accross read_verilog calls
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 92513a244..5b4a4af47 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1016,14 +1016,12 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump flag_icells = icells; flag_autowire = autowire; - std::vector<AstNode*> global_decls; - log_assert(current_ast->type == AST_DESIGN); for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) { if ((*it)->type == AST_MODULE) { - for (auto n : global_decls) + for (auto n : design->verilog_globals) (*it)->children.push_back(n->clone()); for (auto n : design->verilog_packages){ @@ -1054,7 +1052,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump else if ((*it)->type == AST_PACKAGE) design->verilog_packages.push_back((*it)->clone()); else - global_decls.push_back(*it); + design->verilog_globals.push_back((*it)->clone()); } } |