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| author | Clifford Wolf <clifford@clifford.at> | 2016-09-07 00:28:01 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-09-07 00:28:01 +0200 |
| commit | ab18e9df7c55581a9713a332af425011793106a7 (patch) | |
| tree | 78a21c49e64e93a36955b797974fe828f3cfa989 /frontends/ast | |
| parent | f3f5a0204542da3b49e88bcf0b461b6476d45d63 (diff) | |
| download | yosys-ab18e9df7c55581a9713a332af425011793106a7.tar.gz yosys-ab18e9df7c55581a9713a332af425011793106a7.tar.bz2 yosys-ab18e9df7c55581a9713a332af425011793106a7.zip | |
Added assertpmux
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 03596411f..d00738ecd 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -458,6 +458,7 @@ struct AST_INTERNAL::ProcessGenerator case AST_CASE: { RTLIL::SwitchRule *sw = new RTLIL::SwitchRule; + sw->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum); sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap()); current_case->switches.push_back(sw); |