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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-08-29 21:07:34 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-29 21:07:34 +0300 |
| commit | d360693040dda29aba4ef2583e522c6ab88a4961 (patch) | |
| tree | 3de073925c8e3a4a613303ea807aeef12949a3d7 /frontends/ast | |
| parent | d588c6898fb7cfebe52a71a48d6fb21d1623e61b (diff) | |
| parent | b8a9f73089234ed699a4057b50fd739a90abea43 (diff) | |
| download | yosys-d360693040dda29aba4ef2583e522c6ab88a4961.tar.gz yosys-d360693040dda29aba4ef2583e522c6ab88a4961.tar.bz2 yosys-d360693040dda29aba4ef2583e522c6ab88a4961.zip | |
Merge pull request #3 from YosysHQ/Sergey/tests_ice40
Merge my changes to tests_ice40 branch
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 5 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 5 |
2 files changed, 9 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 0d6626b19..82283fb5b 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1502,7 +1502,10 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString rewrite_parameter: para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id]))); delete child->children.at(0); - if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0) + if ((parameters[para_id].flags & RTLIL::CONST_FLAG_REAL) != 0) { + child->children[0] = new AstNode(AST_REALVALUE); + child->children[0]->realvalue = std::stod(parameters[para_id].decode_string()); + } else if ((parameters[para_id].flags & RTLIL::CONST_FLAG_STRING) != 0) child->children[0] = AstNode::mkconst_str(parameters[para_id].decode_string()); else child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 54b9efaad..86dd80c65 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -150,6 +150,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, reg->str = stringf("%s[%d]", node->str.c_str(), i); reg->is_reg = true; reg->is_signed = node->is_signed; + for (auto &it : node->attributes) + if (it.first != ID(mem2reg)) + reg->attributes.emplace(it.first, it.second->clone()); + reg->filename = node->filename; + reg->linenum = node->linenum; children.push_back(reg); while (reg->simplify(true, false, false, 1, -1, false, false)) { } } |