Added log_warning() API

2 files changed, 10 insertions, 10 deletions

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 68c45179d..4a102370b 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -869,7 +869,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_REALVALUE:
 		{
 			RTLIL::SigSpec sig = realAsConst(width_hint);
-			log("Warning: converting real value %e to binary %s at %s:%d.\n",
+			log_warning("converting real value %e to binary %s at %s:%d.\n",
 					realvalue, log_signal(sig), filename.c_str(), linenum);
 			return sig;
 		}
@@ -890,7 +890,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
 				wire->name = str;
 				if (flag_autowire)
-					log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+					log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
 				else
 					log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum);
 			}
@@ -955,10 +955,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
 					if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
 						if (chunk.width == 1)
-							log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
+							log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
 									str.c_str(), filename.c_str(), linenum);
 						else
-							log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
+							log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
 									str.c_str(), filename.c_str(), linenum, chunk.width);
 						chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
 					} else {
@@ -972,10 +972,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 							chunk.offset += add_undef_bits_lsb;
 						}
 						if (add_undef_bits_lsb)
-							log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
+							log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
 									str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb);
 						if (add_undef_bits_msb)
-							log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
+							log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
 									str.c_str(), filename.c_str(), linenum, add_undef_bits_msb);
 					}
 				}
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index d8fdb4c5e..a78fafbd1 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -102,7 +102,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 			verbose_activate:
 				if (mem2reg_set.count(mem) == 0) {
-					log("Warning: Replacing memory %s with list of registers.", mem->str.c_str());
+					log_warning("Replacing memory %s with list of registers.", mem->str.c_str());
 					bool first_element = true;
 					for (auto &place : mem2reg_places[it.first]) {
 						log("%s%s", first_element ? " See " : ", ", place.c_str());
@@ -648,7 +648,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			int width = children[1]->range_left - children[1]->range_right + 1;
 			if (children[0]->type == AST_REALVALUE) {
 				RTLIL::Const constvalue = children[0]->realAsConst(width);
-				log("Warning: converting real value %e to binary %s at %s:%d.\n",
+				log_warning("converting real value %e to binary %s at %s:%d.\n",
 						children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum);
 				delete children[0];
 				children[0] = mkconst_bits(constvalue.bits, sign_hint);
@@ -690,7 +690,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			}
 		}
 		if (current_scope.count(str) == 0) {
-			// log("Warning: Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str());
+			// log_warning("Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str());
 			AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
 			auto_wire->str = str;
 			current_ast_mod->children.push_back(auto_wire);
@@ -1260,7 +1260,7 @@ skip_dynamic_range_lvalue_expansion:;
 		std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
 
 		if (type == AST_ASSIGN_EQ)
-			log("Warning: Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n",
+			log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n",
 					filename.c_str(), linenum);
 
 		int mem_width, mem_size, addr_bits;