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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 16:48:29 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-08 20:16:29 +0100 |
| commit | 89c74ffd7189d4898feb476ff70376385d516eb2 (patch) | |
| tree | 89b1c5f786bc79da9e48ed59e8a33f66088ea523 /frontends/blif | |
| parent | 4e03865d5bf3fafe0bd3735c88431675d53d2663 (diff) | |
| download | yosys-89c74ffd7189d4898feb476ff70376385d516eb2.tar.gz yosys-89c74ffd7189d4898feb476ff70376385d516eb2.tar.bz2 yosys-89c74ffd7189d4898feb476ff70376385d516eb2.zip | |
verilog: Use proc memory writes in the frontend.
Diffstat (limited to 'frontends/blif')
0 files changed, 0 insertions, 0 deletions