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| author | whitequark <whitequark@whitequark.org> | 2020-06-04 11:23:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-04 11:23:06 +0000 |
| commit | 3bffd09d6423b70ca154527c363985ff048f807d (patch) | |
| tree | 5d38c0618e478722d8dcd0fb681ef443869f0b8c /frontends/json/jsonparse.cc | |
| parent | 44f1e651558c5063b6e0c4496d916abc23329751 (diff) | |
| parent | adb483ddfd3163a4efa08e09a35dd926377aa71d (diff) | |
| download | yosys-3bffd09d6423b70ca154527c363985ff048f807d.tar.gz yosys-3bffd09d6423b70ca154527c363985ff048f807d.tar.bz2 yosys-3bffd09d6423b70ca154527c363985ff048f807d.zip | |
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
Diffstat (limited to 'frontends/json/jsonparse.cc')
| -rw-r--r-- | frontends/json/jsonparse.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 7aceffbfc..8ae7c6578 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -309,6 +309,12 @@ void json_import(Design *design, string &modname, JsonNode *node) port_wire->upto = val->data_number != 0; } + if (port_node->data_dict.count("signed") != 0) { + JsonNode *val = port_node->data_dict.at("signed"); + if (val->type == 'N') + port_wire->is_signed = val->data_number != 0; + } + if (port_node->data_dict.count("offset") != 0) { JsonNode *val = port_node->data_dict.at("offset"); if (val->type == 'N') @@ -573,4 +579,3 @@ struct JsonFrontend : public Frontend { } JsonFrontend; YOSYS_NAMESPACE_END - |