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| author | Miodrag Milanović <mmicko@gmail.com> | 2020-11-25 19:15:11 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-11-25 19:15:11 +0100 |
| commit | 180a8e5a45358b4d2c9b599e6838093fd121f9fd (patch) | |
| tree | b04fa3c12e34684b72ed0f416439203288472900 /frontends/rtlil/rtlil_lexer.l | |
| parent | cf67e6a3977410e039d62a1e9f6c49c42cb97b08 (diff) | |
| parent | 7b093dca10707443d8517504fad7f5afa9eea6ca (diff) | |
| download | yosys-180a8e5a45358b4d2c9b599e6838093fd121f9fd.tar.gz yosys-180a8e5a45358b4d2c9b599e6838093fd121f9fd.tar.bz2 yosys-180a8e5a45358b4d2c9b599e6838093fd121f9fd.zip | |
Merge pull request #2453 from YosysHQ/mmicko/verilog_assignments
Generate only simple assignments in verilog backend
Diffstat (limited to 'frontends/rtlil/rtlil_lexer.l')
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