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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-22 11:58:51 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-22 11:58:51 +0200 |
| commit | 2785aaffeb66575128da1f68044dd317660e0f3b (patch) | |
| tree | 864b248092eaa6a8096ecb45ba7fc5438d1af034 /frontends/verific/example.sv | |
| parent | b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb (diff) | |
| download | yosys-2785aaffeb66575128da1f68044dd317660e0f3b.tar.gz yosys-2785aaffeb66575128da1f68044dd317660e0f3b.tar.bz2 yosys-2785aaffeb66575128da1f68044dd317660e0f3b.zip | |
Improve docs for verific bindings, add simply sby example
Diffstat (limited to 'frontends/verific/example.sv')
| -rw-r--r-- | frontends/verific/example.sv | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/frontends/verific/example.sv b/frontends/verific/example.sv new file mode 100644 index 000000000..21a5d42c8 --- /dev/null +++ b/frontends/verific/example.sv @@ -0,0 +1,18 @@ +module top ( + input clk, rst, + output reg [3:0] cnt +); + initial cnt = 0; + + always @(posedge clk) begin + if (rst) + cnt <= 0; + else + cnt <= cnt + 4'd 1; + end + + always @(posedge clk) begin + assume (cnt != 10); + assert (cnt != 15); + end +endmodule |