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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-11 16:07:29 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-12-12 19:56:50 +0100 |
| commit | 0aad88a2fb23e5481538122e1bd4c0fac9ba5e90 (patch) | |
| tree | 707e70353574c9d21e903810e6e8823727e21a15 /frontends/verific/verific.cc | |
| parent | bdc6ba019ca12a3f3d4cfb1a4d64652538b7c5ef (diff) | |
| download | yosys-0aad88a2fb23e5481538122e1bd4c0fac9ba5e90.tar.gz yosys-0aad88a2fb23e5481538122e1bd4c0fac9ba5e90.tar.bz2 yosys-0aad88a2fb23e5481538122e1bd4c0fac9ba5e90.zip | |
Add clean_zerowidth pass, use it for Verilog output.
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.
See #3103.
Diffstat (limited to 'frontends/verific/verific.cc')
0 files changed, 0 insertions, 0 deletions