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| author | Peter Crozier <peter@crozier.com> | 2020-06-03 17:19:28 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-03 17:19:28 +0100 |
| commit | 0d3f7ea011288e1a1fadd4ae27f1e8a57d729053 (patch) | |
| tree | 07bde0d9f492233728070234aed2abd45fbd464d /frontends/verific/verific.cc | |
| parent | 17f050d3c6b8934141c42f96a3418de67a687b2c (diff) | |
| parent | 46ed0db2ec883a4ce330c81f321511e36e35c0b3 (diff) | |
| download | yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.tar.gz yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.tar.bz2 yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.zip | |
Merge branch 'master' into struct
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fe4bda68e..cb0368fd5 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -974,6 +974,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se module->memories[memory->name] = memory; int number_of_bits = net->Size(); + number_of_bits = 1 << ceil_log2(number_of_bits); int bits_in_word = number_of_bits; FOREACH_PORTREF_OF_NET(net, si, pr) { if (pr->GetInst()->Type() == OPER_READ_PORT) { @@ -1265,9 +1266,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->OutputSize()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0) - log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); - for (int i = 0; i < numchunks; i++) { RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; @@ -1295,9 +1293,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se int numchunks = int(inst->Input2Size()) / memory->width; int chunksbits = ceil_log2(numchunks); - if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0) - log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); - for (int i = 0; i < numchunks; i++) { RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)}; |