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| author | Miodrag Milanović <mmicko@gmail.com> | 2023-01-23 16:24:22 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-23 16:24:22 +0100 |
| commit | 245884a1011fe45b00bbb9cacd0111eb014adadf (patch) | |
| tree | d1bcd1f90dc656bef8409bd5f7a677c8d4e4aa35 /frontends/verific/verific.cc | |
| parent | 9bc9121b9efeeb490ca593f75354457a4e420653 (diff) | |
| parent | 6574553189fb6ccb5d00a0c043671a625672b3d3 (diff) | |
| download | yosys-245884a1011fe45b00bbb9cacd0111eb014adadf.tar.gz yosys-245884a1011fe45b00bbb9cacd0111eb014adadf.tar.bz2 yosys-245884a1011fe45b00bbb9cacd0111eb014adadf.zip | |
Merge pull request #3629 from YosysHQ/micko/clang_fixes
Fixes for some of clang scan-build detected issues
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a93d79c80..8898c4597 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2317,8 +2317,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin const char *lib_name = (prefix) ? prefix->GetName() : 0 ; if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; } - veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0; - top = veri_module->GetName(); + if (lib && module_name) + top = lib->GetModule(module_name->GetName(), 1)->GetName(); } } @@ -2344,6 +2344,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin int i; FOREACH_ARRAY_ITEM(netlists, i, nl) { + if (!nl) continue; if (!top.empty() && nl->CellBaseName() != top) continue; nl->AddAtt(new Att(" \\top", NULL)); @@ -3297,8 +3298,8 @@ struct VerificPass : public Pass { const char *lib_name = (prefix) ? prefix->GetName() : 0 ; if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; } - veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0; - top_mod_names.insert(veri_module->GetName()); + if (lib && module_name) + top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); } } else { log("Adding Verilog module '%s' to elaboration queue.\n", name); @@ -3333,6 +3334,7 @@ struct VerificPass : public Pass { int i; FOREACH_ARRAY_ITEM(netlists, i, nl) { + if (!nl) continue; if (!top_mod_names.count(nl->CellBaseName())) continue; nl->AddAtt(new Att(" \\top", NULL)); |