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| author | clairexen <claire@symbioticeda.com> | 2020-10-02 10:16:23 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-02 10:16:23 +0200 |
| commit | 73cd115e0866f2efea622ba5f54d39a621838baa (patch) | |
| tree | 25a25079521ec6aa4c58db1a13c2093751cb2cb0 /frontends/verific/verific.cc | |
| parent | a1a3e686c7bdd8cff139201ee621f10a4d958ed2 (diff) | |
| parent | 46f0932c4c61aca3ab5332f99a4a60d110b52191 (diff) | |
| download | yosys-73cd115e0866f2efea622ba5f54d39a621838baa.tar.gz yosys-73cd115e0866f2efea622ba5f54d39a621838baa.tar.bz2 yosys-73cd115e0866f2efea622ba5f54d39a621838baa.zip | |
Merge pull request #2396 from YosysHQ/claire/empty-param
Ignore empty parameters in Verilog module instantiations
Diffstat (limited to 'frontends/verific/verific.cc')
0 files changed, 0 insertions, 0 deletions