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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 13:24:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 13:24:28 -0800 |
| commit | 8ef241c6f4a976dca67760c43e820d4e812f2fc2 (patch) | |
| tree | 25f21c29042df1bb9e53faeaf711a2a67a4828c0 /frontends/verific/verific.cc | |
| parent | c761fa49b73e9ad3680b05e89442adb6fb22b543 (diff) | |
| download | yosys-8ef241c6f4a976dca67760c43e820d4e812f2fc2.tar.gz yosys-8ef241c6f4a976dca67760c43e820d4e812f2fc2.tar.bz2 yosys-8ef241c6f4a976dca67760c43e820d4e812f2fc2.zip | |
Revert "write_xaiger to not use module POs but only write outputs if driven"
This reverts commit 0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673.
Diffstat (limited to 'frontends/verific/verific.cc')
0 files changed, 0 insertions, 0 deletions