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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-08 11:50:10 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-08 11:50:10 +0100 |
| commit | b06f547993818224ded59c555345140199f4595f (patch) | |
| tree | 106dbeef7c2b70b48b40313336e0893b898d98e8 /frontends/verific/verific.cc | |
| parent | d186ea7a2d74f859972746e03996e9eddc6a5157 (diff) | |
| download | yosys-b06f547993818224ded59c555345140199f4595f.tar.gz yosys-b06f547993818224ded59c555345140199f4595f.tar.bz2 yosys-b06f547993818224ded59c555345140199f4595f.zip | |
If direction NONE use that from first bit
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index dccdcb482..0548d9cb1 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1112,6 +1112,13 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) { if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) { + if (portbus->GetDir() == DIR_NONE && !wire->port_input && !wire->port_output) { + Port *p = portbus->ElementAtIndex(i); + if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_IN) + wire->port_input = true; + if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_OUT) + wire->port_output = true; + } net = portbus->ElementAtIndex(i)->GetNet(); RTLIL::SigBit bit(wire, i - wire->start_offset); if (net_map.count(net) == 0) |