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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-07-29 15:28:33 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-07-29 15:28:33 +0200 |
| commit | cc02d58194fc6de11f625e670d23cdec814dc366 (patch) | |
| tree | 4b847887c7c4500d6ff0b59e1e06254c5351e5c0 /frontends/verific/verific.cc | |
| parent | dc18bf1969e3550a629ffa4722ad40758fc32535 (diff) | |
| download | yosys-cc02d58194fc6de11f625e670d23cdec814dc366.tar.gz yosys-cc02d58194fc6de11f625e670d23cdec814dc366.tar.bz2 yosys-cc02d58194fc6de11f625e670d23cdec814dc366.zip | |
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Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 0276618b4..632dc51fd 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2354,8 +2354,10 @@ struct VerificPass : public Pass { while (argidx < GetSize(args)) file_names.Insert(args[argidx++].c_str()); - if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) + if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) { + verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); + } verific_import_pending = true; goto check_error; |