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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-23 16:28:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-23 16:28:11 -0700 |
| commit | d3555c667c5057f39e0ea31a518d1f4922f2b2a4 (patch) | |
| tree | 08d6b9edb76fb870289c3c9e7a7fca8d56741d39 /frontends/verific/verific.cc | |
| parent | b048afc3a60984d10da7e4618236b957dab527a8 (diff) | |
| download | yosys-d3555c667c5057f39e0ea31a518d1f4922f2b2a4.tar.gz yosys-d3555c667c5057f39e0ea31a518d1f4922f2b2a4.tar.bz2 yosys-d3555c667c5057f39e0ea31a518d1f4922f2b2a4.zip | |
verific: do not assert if wire not found; warn instead
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ae7fcefa7..89606a5bd 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1162,8 +1162,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (!type_range->IsTypeEnum()) continue; auto wire = module->wire(RTLIL::escape_id(id_name)); - log_assert(wire); - wire->set_string_attribute(ID(wiretype), type_range->GetTypeName()); + if (!wire) { + if (net->IsUserDeclared()) + log_warning("Unable to find imported net '%s'.\n", net->Name()); + continue; + } + wire->set_string_attribute(ID::wiretype, type_range->GetTypeName()); MapIter mj; char *k, *v; |