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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-25 23:42:58 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-01 19:11:29 +0200 |
| commit | ec2a468bd389a8275a9a2584fb475901cc495d03 (patch) | |
| tree | 40a3283653f1fe41e51a1fd61fc41dc329537f15 /frontends/verific/verific.cc | |
| parent | 4451f7f5e9b451a7885259554cd3e9562bbf8f88 (diff) | |
| download | yosys-ec2a468bd389a8275a9a2584fb475901cc495d03.tar.gz yosys-ec2a468bd389a8275a9a2584fb475901cc495d03.tar.bz2 yosys-ec2a468bd389a8275a9a2584fb475901cc495d03.zip | |
backend/verilog: Add alternate mode for transparent read port output.
This mode will be used whenever read port cannot be handled in the
"extract address register" way, ie. whenever it has enable, reset,
init functionality or (in the future) mixed transparency mask.
Diffstat (limited to 'frontends/verific/verific.cc')
0 files changed, 0 insertions, 0 deletions