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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:11:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:11:40 +0200 |
| commit | f092b5014895dc5dc62b8103fcedf94cfa9f85a8 (patch) | |
| tree | 2f09add560746030249fe333e551de2f113bccdb /frontends/verific/verific.cc | |
| parent | bf486002d9a6d976b3d086700ccdcfb0fb70ba0b (diff) | |
| download | yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.tar.gz yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.tar.bz2 yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.zip | |
Renamed $_INV_ cell type to $_NOT_
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 1ffcc4229..95b3c407e 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -162,7 +162,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, if (inst->Type() == PRIM_NAND) { RTLIL::SigSpec tmp = module->addWire(NEW_ID); module->addAndGate(NEW_ID, net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), tmp); - module->addInvGate(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput())); + module->addNotGate(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput())); return true; } @@ -174,7 +174,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, if (inst->Type() == PRIM_NOR) { RTLIL::SigSpec tmp = module->addWire(NEW_ID); module->addOrGate(NEW_ID, net_map.at(inst->GetInput1()), net_map.at(inst->GetInput2()), tmp); - module->addInvGate(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput())); + module->addNotGate(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetOutput())); return true; } @@ -184,7 +184,7 @@ static bool import_netlist_instance_gates(RTLIL::Module *module, std::map<Net*, } if (inst->Type() == PRIM_INV) { - module->addInvGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); + module->addNotGate(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetInput()), net_map.at(inst->GetOutput())); return true; } |