Merge pull request #3097 from YosysHQ/modport

If direction NONE use that from first bit

1 files changed, 12 insertions, 2 deletions

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index dccdcb482..2f5e8cb9a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1105,18 +1105,28 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
 		import_attributes(wire->attributes, portbus, nl);
 
-		if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN)
+		bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
+		if (portbus_input)
 			wire->port_input = true;
 		if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_OUT)
 			wire->port_output = true;
 
 		for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) {
 			if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) {
+				bool bit_input = portbus_input;
+				if (portbus->GetDir() == DIR_NONE)  {
+					Port *p = portbus->ElementAtIndex(i);
+					bit_input = p->GetDir() == DIR_INOUT || p->GetDir() == DIR_IN;
+					if (bit_input)
+						wire->port_input = true;
+					if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_OUT)
+						wire->port_output = true;
+				}
 				net = portbus->ElementAtIndex(i)->GetNet();
 				RTLIL::SigBit bit(wire, i - wire->start_offset);
 				if (net_map.count(net) == 0)
 					net_map[net] = bit;
-				else if (wire->port_input)
+				else if (bit_input)
 					module->connect(net_map_at(net), bit);
 				else
 					module->connect(bit, net_map_at(net));