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authorClaire Xenia Wolf <claire@clairexen.net>2021-10-08 16:21:25 +0200
committerClaire Xenia Wolf <claire@clairexen.net>2021-10-08 16:21:25 +0200
commit1602a0386419495993f25667c7c6e5fb55010592 (patch)
tree141013c246c52a430be7f8604664aafcbe09b2ea /frontends/verific/verific.h
parent772b9a108a7370f090790e1887585cfabbf11ac7 (diff)
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Add support for $aldff flip-flops to verific importer
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'frontends/verific/verific.h')
-rw-r--r--frontends/verific/verific.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index f79d8042a..9d5beb787 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -50,6 +50,7 @@ struct VerificClocking {
RTLIL::Cell *addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value = Const());
RTLIL::Cell *addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value);
RTLIL::Cell *addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q);
+ RTLIL::Cell *addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::SigSpec sig_adata, SigSpec sig_d, SigSpec sig_q);
bool property_matches_sequence(const VerificClocking &seq) const {
if (clock_net != seq.clock_net)