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| author | Claire Xen <claire@clairexen.net> | 2021-10-11 10:01:56 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-10-11 10:01:56 +0200 |
| commit | 2d3c79458dab544556a135ddc5fe6ed654d5a41c (patch) | |
| tree | 15b43f491752b1212eebc649fbe4a1bf810cc9f6 /frontends/verific/verific.h | |
| parent | d5cc3a1c72085da29dcc2ef926f885421bb0f2a6 (diff) | |
| parent | c8074769b081f26b2129910502dd9031acd01a2a (diff) | |
| download | yosys-2d3c79458dab544556a135ddc5fe6ed654d5a41c.tar.gz yosys-2d3c79458dab544556a135ddc5fe6ed654d5a41c.tar.bz2 yosys-2d3c79458dab544556a135ddc5fe6ed654d5a41c.zip | |
Merge pull request #3039 from YosysHQ/claire/verific_aldff
Add support for $aldff flip-flops to verific importer
Diffstat (limited to 'frontends/verific/verific.h')
| -rw-r--r-- | frontends/verific/verific.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index f79d8042a..9d5beb787 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -50,6 +50,7 @@ struct VerificClocking { RTLIL::Cell *addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const init_value = Const()); RTLIL::Cell *addAdff(IdString name, RTLIL::SigSpec sig_arst, SigSpec sig_d, SigSpec sig_q, Const arst_value); RTLIL::Cell *addDffsr(IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, SigSpec sig_d, SigSpec sig_q); + RTLIL::Cell *addAldff(IdString name, RTLIL::SigSpec sig_aload, RTLIL::SigSpec sig_adata, SigSpec sig_d, SigSpec sig_q); bool property_matches_sequence(const VerificClocking &seq) const { if (clock_net != seq.clock_net) |