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author | Miodrag Milanović <mmicko@gmail.com> | 2022-03-30 11:03:14 +0200 |
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committer | GitHub <noreply@github.com> | 2022-03-30 11:03:14 +0200 |
commit | 72e5498bdf12fe841ad0468ea586919965165e36 (patch) | |
tree | 8eb197df8921606bdf306cb5a00dea645175a059 /frontends/verific/verific.h | |
parent | c662fcbc5c49dac1caf8b845b6ca3b4c2d8f2c4a (diff) | |
parent | 703769e4942f3fa937118756182868dc47383ba1 (diff) | |
download | yosys-72e5498bdf12fe841ad0468ea586919965165e36.tar.gz yosys-72e5498bdf12fe841ad0468ea586919965165e36.tar.bz2 yosys-72e5498bdf12fe841ad0468ea586919965165e36.zip |
Merge pull request #3250 from YosysHQ/micko/verific_consistent
Import Verific netlist in consistent order
Diffstat (limited to 'frontends/verific/verific.h')
-rw-r--r-- | frontends/verific/verific.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 9d5beb787..416b26396 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -94,7 +94,7 @@ struct VerificImporter void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol); void merge_past_ffs(pool<RTLIL::Cell*> &candidates); - void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo, bool norename = false); + void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::map<std::string,Verific::Netlist*> &nl_todo, bool norename = false); }; void verific_import_sva_assert(VerificImporter *importer, Verific::Instance *inst); |