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| author | Jannis Harder <me@jix.one> | 2022-05-03 13:22:18 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-05-03 14:13:08 +0200 |
| commit | 96f64f4788ca64adde55421a6abadefd182d9a1a (patch) | |
| tree | b3c7faecdbcf26b4b7357024994719f3c06869e9 /frontends/verific/verific.h | |
| parent | 11e75bc27ceacb909c31fc201110f78ee995f979 (diff) | |
| download | yosys-96f64f4788ca64adde55421a6abadefd182d9a1a.tar.gz yosys-96f64f4788ca64adde55421a6abadefd182d9a1a.tar.bz2 yosys-96f64f4788ca64adde55421a6abadefd182d9a1a.zip | |
verific: Fix conditions of SVAs with explicit clocks within procedures
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
Diffstat (limited to 'frontends/verific/verific.h')
| -rw-r--r-- | frontends/verific/verific.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 416b26396..695c04f3b 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -44,6 +44,7 @@ struct VerificClocking { SigBit disable_sig = State::S0; bool posedge = true; bool gclk = false; + bool cond_pol = true; VerificClocking() { } VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false); |