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| author | Jannis Harder <me@jix.one> | 2022-05-09 16:07:39 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-09 16:07:39 +0200 |
| commit | 5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd (patch) | |
| tree | fa7a31d02a6de07779a4f7b7934fb662c5efc06d /frontends/verific/verificsva.cc | |
| parent | d562bfd165b3c107abf717d2661c44aa2b7740fb (diff) | |
| parent | 96f64f4788ca64adde55421a6abadefd182d9a1a (diff) | |
| download | yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.tar.gz yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.tar.bz2 yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.zip | |
Merge pull request #3297 from jix/sva_nested_clk_else
verific: Fix conditions of SVAs with explicit clocks within procedures
Diffstat (limited to 'frontends/verific/verificsva.cc')
| -rw-r--r-- | frontends/verific/verificsva.cc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 1bbdcf016..12bac2a3d 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -1522,10 +1522,13 @@ struct VerificSvaImporter if (inst == nullptr) return false; - if (clocking.cond_net != nullptr) + if (clocking.cond_net != nullptr) { trig = importer->net_map_at(clocking.cond_net); - else + if (!clocking.cond_pol) + trig = module->Not(NEW_ID, trig); + } else { trig = State::S1; + } if (inst->Type() == PRIM_SVA_S_EVENTUALLY || inst->Type() == PRIM_SVA_EVENTUALLY) { @@ -1587,8 +1590,11 @@ struct VerificSvaImporter SigBit trig = State::S1; - if (clocking.cond_net != nullptr) + if (clocking.cond_net != nullptr) { trig = importer->net_map_at(clocking.cond_net); + if (!clocking.cond_pol) + trig = module->Not(NEW_ID, trig); + } if (inst == nullptr) { |