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authorJim Lawson <ucbjrl@berkeley.edu>2019-08-07 10:14:45 -0700
committerJim Lawson <ucbjrl@berkeley.edu>2019-08-07 10:14:45 -0700
commit5e8a98c8fd5f31b514748676804dd1237bce4225 (patch)
treeead2b0029b55e078abc1023c434b87b4684ba498 /frontends/verific
parent7e298084e458c3fcccece565df305271db51aec8 (diff)
parent5545cd3c108ef240ccf6278b2734412acf81cd2a (diff)
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Merge branch 'master' into firrtl_err_on_unsupported_cell
# Conflicts: # backends/firrtl/firrtl.cc
Diffstat (limited to 'frontends/verific')
-rw-r--r--frontends/verific/verific.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 2bf99e58e..06d58a44a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2484,7 +2484,7 @@ struct ReadPass : public Pass {
args[0] = "verific";
} else {
args[0] = "read_verilog";
- args.erase(args.begin()+1, args.begin()+2);
+ args[1] = "-defer";
}
Pass::call(design, args);
return;
@@ -2498,6 +2498,7 @@ struct ReadPass : public Pass {
if (args[1] == "-formal")
args.insert(args.begin()+1, std::string());
args[1] = "-sv";
+ args.insert(args.begin()+1, "-defer");
}
Pass::call(design, args);
return;