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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-17 01:56:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-17 01:56:00 +0100 |
| commit | a67cd2d4a284cb945af6d477cc215cef7bdd22a8 (patch) | |
| tree | 2be5f13ffe5ecdec4fc365bba955ccd83258254c /frontends/verific | |
| parent | acda74c12cd39ae1a17d15f472728b49ad584e91 (diff) | |
| download | yosys-a67cd2d4a284cb945af6d477cc215cef7bdd22a8.tar.gz yosys-a67cd2d4a284cb945af6d477cc215cef7bdd22a8.tar.bz2 yosys-a67cd2d4a284cb945af6d477cc215cef7bdd22a8.zip | |
Progress in Verific bindings
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8b42ca8c1..84e5e6736 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -429,6 +429,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist* import_attributes(wire->attributes, port); module->add(wire); + wire->port_id = nl->IndexOf(port) + 1; + if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_IN) wire->port_input = true; if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_OUT) |