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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-26 13:50:14 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-26 13:50:14 +0200 |
| commit | 2c04d883b16ade4acfaa9e50b5c29ca206fdfcbb (patch) | |
| tree | fc5e35f23c353d83a234a824a97ff038f6edd747 /frontends/verilog/Makefile.inc | |
| parent | cb1d439d1069e20b8f28d9f3e08c69c1dbcae1c1 (diff) | |
| download | yosys-2c04d883b16ade4acfaa9e50b5c29ca206fdfcbb.tar.gz yosys-2c04d883b16ade4acfaa9e50b5c29ca206fdfcbb.tar.bz2 yosys-2c04d883b16ade4acfaa9e50b5c29ca206fdfcbb.zip | |
Minor coding style fix
Diffstat (limited to 'frontends/verilog/Makefile.inc')
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