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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-06-22 06:03:36 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-07-01 19:51:47 +0000 |
| commit | 3eb2593876b3778d158b1955aa5a2b4bf40aab5a (patch) | |
| tree | 5e11062f49f21de56b2834a45c2b8cf433cb2308 /frontends/verilog/Makefile.inc | |
| parent | 8cb1a86c23a8d9abbaadc1e7400018a593e2e818 (diff) | |
| download | yosys-3eb2593876b3778d158b1955aa5a2b4bf40aab5a.tar.gz yosys-3eb2593876b3778d158b1955aa5a2b4bf40aab5a.tar.bz2 yosys-3eb2593876b3778d158b1955aa5a2b4bf40aab5a.zip | |
glift: Add support for $_NAND_ and $_NOR_ cells.
Diffstat (limited to 'frontends/verilog/Makefile.inc')
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