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| author | whitequark <whitequark@whitequark.org> | 2020-07-09 20:17:19 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-09 20:17:19 +0000 |
| commit | c0bcbe1f6254f050207a91506a63aa9d784bd8d6 (patch) | |
| tree | a788116d9cbdfe717123327895ea8a565a12ee39 /frontends/verilog/Makefile.inc | |
| parent | 0e9b889b77454ce8bcee47e73ed9b79f9b31771f (diff) | |
| parent | dc35ef05f93bf634e7f158869af48707233505e2 (diff) | |
| download | yosys-c0bcbe1f6254f050207a91506a63aa9d784bd8d6.tar.gz yosys-c0bcbe1f6254f050207a91506a63aa9d784bd8d6.tar.bz2 yosys-c0bcbe1f6254f050207a91506a63aa9d784bd8d6.zip | |
Merge pull request #2255 from whitequark/bison-Werror-conflicts
verilog_parser: turn S/R and R/R conflicts into hard errors
Diffstat (limited to 'frontends/verilog/Makefile.inc')
| -rw-r--r-- | frontends/verilog/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc index cf9b9531e..d5d5edd3d 100644 --- a/frontends/verilog/Makefile.inc +++ b/frontends/verilog/Makefile.inc @@ -6,7 +6,7 @@ GENFILES += frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y $(Q) mkdir -p $(dir $@) - $(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $< + $(P) $(BISON) -Werror=conflicts-sr,error=conflicts-rr -o $@ -d -r all -b frontends/verilog/verilog_parser $< frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc |