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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-26 01:52:59 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-26 01:52:59 +0200 |
| commit | 2cc09161ffd774430293dfd18e307e75bea73c5e (patch) | |
| tree | 9c018ea7954daddaaa8e6cc89502ed522f3a30a9 /frontends/verilog/const2ast.cc | |
| parent | 143c0abd33ed76b2a7e38dbbac1767e6f7edd68f (diff) | |
| download | yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.tar.gz yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.tar.bz2 yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.zip | |
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
Diffstat (limited to 'frontends/verilog/const2ast.cc')
0 files changed, 0 insertions, 0 deletions