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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 14:48:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 14:48:35 -0700 |
| commit | 812469aaa351792a5215ed871de59b544934f5e5 (patch) | |
| tree | 4b03037dcf606b19f908e3ec6fce616fe13a2eee /frontends/verilog/const2ast.cc | |
| parent | c762be593042ed5d812a3a37d494a82565cbaad0 (diff) | |
| parent | b2b5cf78e21def63c54c080217d77afefba8e4c7 (diff) | |
| download | yosys-812469aaa351792a5215ed871de59b544934f5e5.tar.gz yosys-812469aaa351792a5215ed871de59b544934f5e5.tar.bz2 yosys-812469aaa351792a5215ed871de59b544934f5e5.zip | |
Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
Diffstat (limited to 'frontends/verilog/const2ast.cc')
| -rw-r--r-- | frontends/verilog/const2ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 3a3634d34..f6a17b242 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -153,7 +153,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn { if (warn_z) { AstNode *ret = const2ast(code, case_type); - if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) + if (ret != nullptr && std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n", current_filename.c_str(), get_line_num()); return ret; |