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author | Clifford Wolf <clifford@clifford.at> | 2015-08-17 16:22:53 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-08-17 16:22:53 +0200 |
commit | a7ab9172f9f003a0552c9f6e7d8df7729bc1dbbb (patch) | |
tree | 186fd3ce5f959f803d416b5d56fe9b2406dffc8b /frontends/verilog/const2ast.cc | |
parent | 04910428491f249b79f7974f118b8e01579b2a51 (diff) | |
download | yosys-a7ab9172f9f003a0552c9f6e7d8df7729bc1dbbb.tar.gz yosys-a7ab9172f9f003a0552c9f6e7d8df7729bc1dbbb.tar.bz2 yosys-a7ab9172f9f003a0552c9f6e7d8df7729bc1dbbb.zip |
Small corrections to const2ast warning messages
Diffstat (limited to 'frontends/verilog/const2ast.cc')
-rw-r--r-- | frontends/verilog/const2ast.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 5bc8c700e..9cc99750f 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -142,7 +142,7 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le } if (len > len_in_bits) - log_warning("(Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n", + log_warning("Literal has a width of %d bit, but value requires %d bit. (%s:%d)\n", len_in_bits, len, current_filename.c_str(), get_line_num()); } @@ -152,7 +152,7 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn if (warn_z) { AstNode *ret = const2ast(code, case_type); if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end()) - log_warning("Yosys does not support tri-state logic at the moment. (%s:%d)\n", + log_warning("Yosys has only limited support for tri-state logic at the moment. (%s:%d)\n", current_filename.c_str(), get_line_num()); return ret; } |