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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-13 15:57:17 -0700 |
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| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-09-14 10:26:43 -0700 |
| commit | c8f2f082c6e20a50ca7efe8c5a67d26f2e24a4ab (patch) | |
| tree | d5b656a0fe126c568906810072e59740b30694a5 /frontends/verilog/const2ast.cc | |
| parent | 122532b7e137a53a91be155668687246a25d27e7 (diff) | |
| download | yosys-c8f2f082c6e20a50ca7efe8c5a67d26f2e24a4ab.tar.gz yosys-c8f2f082c6e20a50ca7efe8c5a67d26f2e24a4ab.tar.bz2 yosys-c8f2f082c6e20a50ca7efe8c5a67d26f2e24a4ab.zip | |
Added support for inferring counters with reset to full scale instead of zero
Diffstat (limited to 'frontends/verilog/const2ast.cc')
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