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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-17 14:28:52 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-17 14:28:52 +0100 |
| commit | 02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9 (patch) | |
| tree | e5adb1a2baa9eba28f7c28bf755d00da266bfe52 /frontends/verilog/lexer.l | |
| parent | 0851c2b6ea7044d9bce2014a2be2365a2bf7e1b0 (diff) | |
| download | yosys-02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9.tar.gz yosys-02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9.tar.bz2 yosys-02e6f2c5be8c5514cc8cdb7b3344f6170fb87af9.zip | |
Added Verilog support for "`default_nettype none"
Diffstat (limited to 'frontends/verilog/lexer.l')
| -rw-r--r-- | frontends/verilog/lexer.l | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l index 81167cf4e..79f44b4a6 100644 --- a/frontends/verilog/lexer.l +++ b/frontends/verilog/lexer.l @@ -81,6 +81,18 @@ namespace VERILOG_FRONTEND { "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */ +"`default_nettype"[ \t]+[^ \t\r\n/]+ { + char *p = yytext; + while (*p != 0 && *p != ' ' && *p != '\t') p++; + while (*p == ' ' || *p == '\t') p++; + if (!strcmp(p, "none")) + VERILOG_FRONTEND::default_nettype_wire = false; + else if (!strcmp(p, "wire")) + VERILOG_FRONTEND::default_nettype_wire = true; + else + frontend_verilog_yyerror("Unsupported default nettype: %s", p); +} + "`"[a-zA-Z_$][a-zA-Z0-9_$]* { frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext); } |