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author | Clifford Wolf <clifford@clifford.at> | 2014-06-12 11:54:20 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-06-12 11:54:20 +0200 |
commit | 482d9208aa9dacb7afe21f08c882d4881581013a (patch) | |
tree | a5a4d409f7d84cc2dc6283dcf45df3aea02cb061 /frontends/verilog/lexer.l | |
parent | 9a6cd64fc2ca46c9aed1bd03b6898c7734420c53 (diff) | |
download | yosys-482d9208aa9dacb7afe21f08c882d4881581013a.tar.gz yosys-482d9208aa9dacb7afe21f08c882d4881581013a.tar.bz2 yosys-482d9208aa9dacb7afe21f08c882d4881581013a.zip |
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
Diffstat (limited to 'frontends/verilog/lexer.l')
-rw-r--r-- | frontends/verilog/lexer.l | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l index 5300d1b26..8f4b49916 100644 --- a/frontends/verilog/lexer.l +++ b/frontends/verilog/lexer.l @@ -52,6 +52,14 @@ namespace VERILOG_FRONTEND { std::vector<int> ln_stack; } +#define SV_KEYWORD(_tok) \ + if (sv_mode) return _tok; \ + log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\ + "recognized unless read_verilog is called with -sv!\n", yytext, \ + AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); \ + frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \ + return TOK_ID; + %} %option yylineno @@ -143,7 +151,14 @@ namespace VERILOG_FRONTEND { "while" { return TOK_WHILE; } "repeat" { return TOK_REPEAT; } -"assert"([ \t\r\n]+"property")? { return TOK_ASSERT; } +"always_comb" { SV_KEYWORD(TOK_ALWAYS); } +"always_ff" { SV_KEYWORD(TOK_ALWAYS); } +"always_latch" { SV_KEYWORD(TOK_ALWAYS); } + +"assert" { SV_KEYWORD(TOK_ASSERT); } +"property" { SV_KEYWORD(TOK_PROPERTY); } +"logic" { SV_KEYWORD(TOK_REG); } +"bit" { SV_KEYWORD(TOK_REG); } "input" { return TOK_INPUT; } "output" { return TOK_OUTPUT; } |