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| author | Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at> | 2013-01-08 09:31:31 +0100 |
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| committer | Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at> | 2013-01-08 09:43:35 +0100 |
| commit | 4f6cda502d8633068ebd137bbeb6cbc6bfabf938 (patch) | |
| tree | 3f99060acda83bee70411d69a0b7503a3c2aff90 /frontends/verilog/parser.y | |
| parent | bc630ba0fa249c09d4f3fb5ef48eb6d573a21879 (diff) | |
| download | yosys-4f6cda502d8633068ebd137bbeb6cbc6bfabf938.tar.gz yosys-4f6cda502d8633068ebd137bbeb6cbc6bfabf938.tar.bz2 yosys-4f6cda502d8633068ebd137bbeb6cbc6bfabf938.zip | |
Add support for "fsm_export" synthesis attributes to fsm_export pass.
This allows to specify the file name for exported files directly in the HDL
source via the fsm_export=... attribute on the FSM state register.
Verilog example:
(* fsm_export="my_fsm.kiss2" *)
reg [3:0] state;
The fsm_export pass now also accepts the option "-noauto". This causes only
FSMs with the fsm_export attribute to be exported, any other FSMs are ignored.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
Diffstat (limited to 'frontends/verilog/parser.y')
0 files changed, 0 insertions, 0 deletions