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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-06 06:49:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-06 06:49:07 +0200 |
| commit | 50e2dce5e7b9a193eab90def9b68e4d77b3789ca (patch) | |
| tree | a9f0670b8cf7d3fc215a26b3431dbbd2b9c7db36 /frontends/verilog/preproc.cc | |
| parent | fd8ef128bfdc01b6bcf90ca5a3426aac22811161 (diff) | |
| parent | dd134914cc93f7506504ad95aad438a468bb0fe8 (diff) | |
| download | yosys-50e2dce5e7b9a193eab90def9b68e4d77b3789ca.tar.gz yosys-50e2dce5e7b9a193eab90def9b68e4d77b3789ca.tar.bz2 yosys-50e2dce5e7b9a193eab90def9b68e4d77b3789ca.zip | |
Merge pull request #1072 from YosysHQ/eddie/fix_1069
Error out if no top module given before 'sim'
Diffstat (limited to 'frontends/verilog/preproc.cc')
0 files changed, 0 insertions, 0 deletions